FIG. 14 is a perspective view schematically illustrating a prior art GaAs monolithic microwave integrated circuit (hereinafter referred to as a GaAs MMIC). In FIG. 14, the GaAs MMIC includes a semi-insulating GaAs substrate 1 having opposite front and rear surfaces. There are disposed on the front surface of the substrate 1, first and second FETs 21 and 22, first and second MIM (Metal Insulator Metal) capacitors 31 and 32, a diffused resistor 40, first and second signal lines 51a and 51b, and first and second open stubs 52a and 52b for impedance matching. A rear electrode 12 is disposed on the rear surface of the substrate 1. The microwave circuit comprises the above-described active elements, passive elements, and signal lines. The semi-insulating semiconductor substrate 1 may comprise other III-V compound semiconductors, such as InP.
A drain region 1b common to the first and second FETs 21 and 22 is formed in a prescribed region of the GaAs substrate 1, and source regions 1a.sub.1 and 1a.sub.2 of the first and second FETs 21 and 22, respectively, are formed at opposite sides of the common drain region 1b. A drain electrode 2b common to the first and second FETs 21 and 22 is disposed on the common drain region 1b, and source electrodes 2a.sub.1 and 2a.sub.2 are disposed on the source regions 1a.sub.1 and 1a.sub.2, respectively. Gate electrodes 2c.sub.1 and 2c.sub.2 of the FETs 21 and 22 are disposed between the common drain region 1b and the source regions 1a.sub.1 and 1a.sub.2, respectively.
The MIM capacitor 31 (32) comprises a lower electrode 31a (32a), and an upper electrode 31c (32c) having an air-bridge structure disposed on the lower electrode 31a (32a) via an insulating film 31b (32b).
The source electrodes 2a.sub.1 and 2a.sub.2 of the first and second FETs 21 and 22 are connected to each other by an electroplated wiring 210 having an air bridge structure (hereinafter referred to as an air-bridge wiring). Further, the source electrodes 2a.sub.1 and 2a.sub.2 are connected to the rear electrode 12 through via-holes 211a and 212a in which plated wirings 211 and 212 are formed (hereinafter referred to as via-hole wirings).
FIG. 15(a) is a sectional view of a part of the GaAs MMIC 200 in the vicinity of the air-bridge wiring 210 and the via-hole wiring 212. In the figure, the same reference numerals as in FIG. 14 designate the same or corresponding parts. Reference numeral 3a designates a metal film serving as a feeding layer when the air-bridge wiring 210 is formed by electroplating. Reference numeral 3b designates a metal film serving as a feeding layer when the via-hole wiring 212 is formed by electroplating.
In a GaAs MMIC having the above-described structure, improved performance and reduced size are demanded in a key device of, for example, a portable telephone that has been spread in recent years. In order to meet these demands, it is necessary to increase the height of the air-bridge wiring and reduce the size of the air-bridge wiring and the via-hole wiring for high density integration.
For example, when the height of the air-bridge wiring is increased, the capacitance between the air-bridge wiring and a lower wiring that crosses the air-bridge wiring is reduced, increasing the operation speed. When a portion of the air-bridge wiring contacting a lower electrode included in the lower wiring, i.e., a metal post, is reduced in size, the space between adjacent lower wirings is reduced, whereby the length of the wirings is reduced. Consequently, the operation speed of the microwave circuit is increased.
However, it is impossible to form a resist film having a fine pattern of an air-bridge wiring on a substrate having a via-hole or the like that causes a high step.
That is, as illustrated in FIG. 16(a), when the via-hole 212a is formed on the surface of the GaAs substrate 1 where the lower electrodes 2a.sub.1 and 2a.sub.2 are present, a considerable step is produced due to the via-hole 212a. In this case, if a thick resist film 17a is deposited on the surface of the substrate 1 as shown in FIG. 16(b) to avoid imperfect coverage by the resist film, it is difficult to produce minute resist apertures at portions 17a.sub.1 and 17a.sub.2 corresponding to metal posts of the air-bridge wiring. On the other hand, when a resist film 17b having a thickness that ensures improved, i.e., minute, resist apertures 17b.sub.1 and 17b.sub.2 at portions corresponding to the metal posts as shown in FIG. 16(c), the coverage of the resist film 17b is insufficient at the periphery of the via-hole 212a (regions "C" in FIG. 16(c)).
Therefore, in the prior art production method of an MMIC including air-bridge wirings and via-hole wirings, after electroplating of an air-bridge wiring on the substrate, a via-hole that causes a considerable step of the substrate is formed. Thereafter, a wiring layer is electroplated in the via-hole. In addition, for the patterning of the air-bridge wiring, a positive type resist that ensures a large aspect ratio of the resist aperture and that can be minutely patterned is employed. Further, for the patterning of the via-hole, a negative type resist that can be easily removed from the via-hole after the deposition of the resist is employed although it does not ensure an aspect ratio of the resist aperture as large as that of the positive type resist.
Hereinafter, the production method of the prior art GaAs MMIC will be described in more detail, emphasizing process steps of forming the air-bridge wiring and the via-hole wiring of the MMIC.
FIGS. 17(a)-17(f) are sectional views illustrating process steps of forming the air-bridge wiring, FIGS. 18(a)-18(b) are sectional views illustrating process steps of forming the via-hole wiring, and FIGS. 19(a)-19(d) are sectional views illustrating process steps of removing a resist film for selective plating of the via-hole wiring, and process steps on the rear surface of the substrate. In these figures, the same reference numerals as in FIGS. 14 and 15(a) designate the same or corresponding parts.
Initially, as illustrated in FIG. 17(a), active elements, such as FETs, passive elements, such as capacitors and resistors, and signal lines connecting these elements are formed on a semi-insulating GaAs substrate 1. On the front surface of the substrate 1, lower electrodes 2a.sub.1 and 2a.sub.2, such as source electrodes of FETs, and other lower electrodes 2 are present. Each of the lower electrodes is 1 .mu.m.about.2 .mu.m thick and comprises a single Au film or a laminated structure of Ti/Au, Ti/Mo/Au, or Ti/Pt/Au. The Ti layer in the laminated structure ensures a sufficient adhesion between the Au layer in the laminated structure and the lower electrode. In addition, the Mo and Pt layers in the laminated structures of Ti/Mo/Au and Ti/Pt/Au serve as barrier layers that prevent constituent elements of electrodes (not shown) comprising a reactive material and disposed under the lower electrodes from diffusing into an electroplated metal layer to be formed on the lower electrodes. In the lower electrode including an Au layer, the thickness of the uppermost Au layer accounts for 80.about.90 percent of the whole thickness of the lower electrode. In the lower electrode including a Ti layer or an Mo layer, the thickness of the Ti or Mo layer accounts for about 10 percent of the whole thickness of the lower electrode.
Thereafter, a positive type lower resist film 7 is deposited over the entire surface of the substrate to a thickness equivalent to a prescribed height of an air bridge wiring, for example, 1 .mu.m or 3 .mu.m. The lower resist film 7 is patterned to form apertures 7a.sub.1 and 7a.sub.2 at the lower electrodes 2a.sub.1 and 2a.sub.2, respectively (FIG. 17(b)).
In the step of FIG. 17(c), a feeding layer 3a that is used in a subsequent electroplating process is formed on the resist film 7 and in the apertures 7a.sub.1 and 7a.sub.2 of the resist film 7 to a thickness of 1000.about.2000 .ANG. by sputtering or vapor deposition. The feeding layer 3a has a laminated structure, such as Ti/Mo/Au, and the uppermost Au layer accounts for a great part of the laminated structure.
In the step of FIG. 17(d), a positive type upper resist film 9 is deposited on the entire surface of the substrate and patterned to form an aperture 9a at a region of the substrate where an air-bridge wiring is to be formed, i.e., a region between the resist apertures 7a.sub.1 and 7a.sub.2. This upper resist film 9 serves as a mask in the subsequent electroplating process.
In the step of FIG. 17(e), using the upper resist film 9 as a mask, a metal film is selectively electroplated in the resist aperture 9a to a thickness of 1 .mu.m.about.10 .mu.m, forming an air-bridge wiring 210 connecting the lower electrodes 2a.sub.1 and 2a.sub.2. The reason why a positive type resist is employed as the upper resist 9 is that the positive type resist provides good verticality of the side walls of the resist aperture.
Thereafter, using the air-bridge wiring as a mask, the upper resist film 9 is removed with a release solution or ashing (FIG. 17(f)), and the feeding layer 3a is removed by ion milling. Finally, the lower resist film 7 including a portion under the air-bridge wiring 210 is completely removed with a release solution, resulting in a structure shown in FIG. 18(a).
In the step of FIG. 18(b), a positive type resist film 8 is deposited under predetermined conditions, such as the rotation frequency of spin coating, the viscosity of the resist, and the temperature of the applied resist, so that the resist enters the space under the air-bridge wiring 210. Subsequently, the resist film 8 is patterned to form an aperture 8a at a region where a via-hole is to be formed.
Using the resist film 8 as a mask, a via-hole 212a is formed by RIE (Reactive Ion Etching), followed by removal of the resist film 8 with a release solution (FIG. 18(c)).
Thereafter, a negative type lower resist film 10 is deposited to a thickness sufficient to completely cover the air-bridge wiring 210. The lower resist film 10 is patterned to form an aperture 10a opposite the via-hole 212a and the vicinity (FIG. 18(d)). The reason why a negative type resist is used as the lower resist film 10 is that the negative type resist deposited in the via-hole 212a can be completely removed when the resist film is patterned.
In the step of FIG. 18(e), a feeding layer 3b used in a subsequent electroplating process is formed by sputtering. Thereafter, as illustrated in FIG. 18(f), a negative type upper resist film 11 is deposited over the entire surface and patterned to form an aperture 11a on the via-hole 212a. The resist aperture 11a is larger than the resist aperture 10a of the lower resist 10. Using the upper resist film 11 as a mask, a metal film is selectively electroplated in the resist aperture 11a to a thickness of 5 .mu.m to 8 .mu.m, forming a via-hole wiring 212 (FIG. 18(f)).
After removal of the upper resist film 11 with a release solution (FIG. 19(a)), the feeding layer 3b is removed by ion milling, and the lower resist 10 is removed with a release solution (FIG. 19(b)). In this way, the processing on the front surface of the GaAs substrate 1 is completed.
Thereafter, the rear surface of the substrate 1 is etched until the bottom surface of the via-hole wiring 212 is exposed (FIG. 19(c)). Finally, a rear electrode 12 is formed on the rear surface of the substrate 1 to complete the GaAs MMIC 200 shown in FIG. 19(d).
The above-described prior art method illustrated in FIGS. 17(a)-17(f), 18(a)-18(f), and 19(a)-19(d) in which the air-bridge wiring and the via-hole wiring are formed in the different electroplating steps has the following drawbacks.
That is, after the formation of the air-bridge wiring 210 (FIG. 18(c)), the unevenness of the surface of the substrate 1 is considerable. Therefore, in the step of FIGS. 18(d)-18(f), it is difficult to form fine patterns of the lower and upper resist films 10 and 11 which serve as masks for the subsequent selective electroplating of the via-hole wiring 212, with good coverage. Although the coverage can be improved by increasing the thicknesses of the resist films 10 and 11, in this case the resist apertures 10a and 11a have unwanted over-hanging portions or portions of the resist films remain at the bottom of the via-hole 212a. On the other hand, when the resist films 10 and 11 are thin enough to produce fine patterns of the apertures 10a and 11a, the coverage of the resist films is poor at the upper edge of the air-bridge wiring 210.
The poor coverage of the resist films 10 and 11 causes excessive plating of the metal film 212 at the upper edge of the air-bridge wiring 210. Further, when the resist films 10 and 11 remain in the via-hole 212a because of inferior patterning of the resist films, the metal film 212 is plated abnormally in the via-hole 212a.
The above-described troubles in the production process adversely affect the characteristics of the device. For example, the excessive growth of the plated metal causes an increase in the capacitance or a short-circuiting between adjacent plated wirings, and the abnormal growth of the plated metal reduces the reliability of the metal wiring.
Furthermore, in the second electroplating process of the metal wiring 212, it is difficult to connect the metal wiring 212 to the metal wiring 210 formed in the first electroplating process because the adhesion between the plated metals is not sufficient. Therefore, the plated wirings 210 and 2212 are connected through the lower electrode 2a.sub.2 alone as shown in FIG. 15(a). Consequently, the wiring resistance cannot be adequately reduced.
Furthermore, in the structure shown in FIG. 15(b), since a portion 2a.sub.21 of the lower electrode 2a.sub.2 under the air-bridge wiring is separated from a portion 2a.sub.22 of the lower electrode under the via-hole wiring 212, these portions must be connected by an additional lower wiring 2a.sub.3. In this case, in addition to the wiring resistance of the lower wiring 2a.sub.3, contact resistances are produced at the junctions of the lower wiring 2a.sub.3 and the portions 2a.sub.21 and 2a.sub.22 of the lower electrode 2a.sub.2. Consequently, a device with sufficient performance cannot be obtained.
Further, since the air-bridge wiring 210 and the via-hole wiring 212 have different heights on the substrate 1 as shown in FIG. 15(a), when the substrate 1 is etched from the rear surface with the front surface adhered to a support plate (not shown), the holding power is not evenly distributed across the substrate, resulting in cracking or tilting of the substrate. When the substrate tilts, it is difficult to accurately control the thickness of the substrate during the rear etching process.
A description is given of another structure for connecting electroplated wirings, employed in a prior art GaAs MMIC or the like.
FIG. 20 is a sectional view for explaining a structure for connecting a plated air-bridge wiring and an ordinary plated wiring, i.e., a wiring having no air-bridge structure, employed in a prior art GaAs MMIC.
In FIG. 20, reference numeral 1 designates a semi-insulating GaAs substrate having opposite front and rear surfaces. A first lower electrode 2b.sub.1 having a relatively small width and a second lower electrode 2b.sub.2 having a relatively large width are disposed on the front surface of the GaAs substrate 1. The first lower electrode 2b.sub.1 is connected to the second lower electrode 2b.sub.2 through a plated air-bridge wiring 220. Reference numeral 221 designates an ordinary plated metal wiring, such as a signal line. A portion of the plated wiring 221 is disposed on an end of the second lower wiring 2b.sub.2 as a bonding pad. Preferably, the first and second lower electrodes 2b.sub.1 and 2b.sub.2 comprise a single Au layer or a laminated structure of Ti/Au, Ti/Mo/Au, or Ti/Pt/Au.
When used in the GaAs MMIC shown in FIG. 14, the structure shown in FIG. 20 is applicable to a connection between the air-bridge upper electrode 32c of the MIM capacitor 32 and the signal line 51b. Although the air-bridge upper electrode 32c is united with the signal line 51b in FIG. 14, in an actual device the electroplated portion of the air-bridge upper electrode 220 is not connected to the signal line 221. Only the lower electrode 2b.sub.2 is connected to the signal line 221.
The method of producing the prior art GaAs MMIC including the air-bridge wiring 220 and the ordinary metal wiring 221 will be described briefly.
Initially, as illustrated in FIG. 21(a), the lower electrodes 2b.sub.1 and 2b.sub.2 are formed on prescribed regions of the semi-insulating GaAs substrate 1.
In the step of FIG. 21(b), a lower resist film 27 is deposited over the entire surface and patterned by exposure and development techniques to form resist apertures 27a.sub.1 and 27a.sub.2 opposite portions of the lower electrodes 2b.sub.1 and 2b.sub.2 for contact with an air-bridge wiring, and a resist aperture 27a.sub.3 opposite a portion of the lower electrode 2b.sub.2 on which a bonding pad is to be disposed.
Thereafter, as illustrated in FIG. 21(c), a feeding layer 3 for a subsequent electroplating process is deposited to a thickness of 1000.about.2000 .ANG. by sputtering or vapor deposition. Preferably, the feeding layer 3 comprises Ti/Mo/Au.
In the step of FIG. 21(d), a negative type upper resist film 28 is deposited to a thickness equivalent to a prescribed height of an air-bridge wiring. The resist film 28 is patterned to form a resist aperture 28a opposite a region including the lower resist apertures 27a.sub.1 and 27a.sub.2, and a resist aperture 28b opposite a region including the lower resist aperture 27a.sub.3. The upper resist aperture 28b is larger than the lower resist aperture 27a.sub.3.
Using the upper resist film 28 as a mask, a metal film is selectively electroplated in the resist apertures 28a and 28b to a thickness of 1 .mu.m.about.10 .mu.m, forming an air-bridge wiring 220 connecting the lower electrodes 2b.sub.1 and 2b.sub.2, and an ordinary wiring 221 having a portion connected to the lower electrode 2b.sub.2 as a bonding pad (FIG. 22(a)).
Thereafter, the upper resist film 28 is removed by ashing or a release solution (FIG. 22(b)), and the feeding layer 3 is removed by ion milling using the plated wirings 220 and 221 as masks (FIG. 22(c)).
After removal of the lower resist film 27 with a release solution, the rear surface of the substrate 1 is etched and a rear electrode 12 is formed over the rear surface of the substrate 1, completing a GaAs MMIC (FIG. 22(d)).
The above-described prior art method illustrated in FIGS. 21(a)-21(d) and 22(a)-22(d) in which the air-bridge metal wiring 220 and the ordinary metal wiring 221 are formed simultaneously in the same electroplating process has the following drawbacks.
In this prior art method, the lower resist film 27 serves both as a mask for patterning the air-bridge wiring 220 and a mask for patterning the metal wiring 221. Since the thickness of the lower resist film 27 is equivalent to the height of the air-bridge wiring, it exceeds a sufficient thickness of a mask for patterning of the metal wiring 221. In this case, it is very difficult to form a fine pattern of the metal wiring 221 by selective electroplating.
Further, in the region where the metal wiring 221 is formed, since the aperture 28a of the upper resist film 28 is larger than the aperture 27a of the lower resist film 27, the plated metal wiring 221 has a swollen portion 221a at its periphery as shown in FIG. 20. The swollen portion 221a of the plated metal wiring 221 causes considerable unevenness of the surface of the substrate, adversely affecting subsequent processing and assembly. For example, the swollen portion 221a of the metal wiring 221 vibrates and cracks in a vibration test. In addition, the swollen portion 221a is an obstacle when a wire is bonded to the bonding pad of the plated metal wiring 221.
Meanwhile, Japanese Published Patent Application No. Sho. 63-296247 discloses a method of producing metal wirings, in which a fine and thin wiring is produced and a sufficient height of an air-bridge wiring is maintained. In this method, the fine wiring having a prescribed thickness and a lower part of the air-bridge wiring are formed simultaneously in a first electroplating process. Thereafter, in a second electroplating process, a metal layer is selectively plated on the lower part of the air-bridge wiring to form an upper part of the air-bridge wiring, completing the air-bridge wiring. In this method, however, it is impossible to produce a fine and thin wiring and an adequately high air-bridge wiring in only one electroplating step.